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lt3029 1 3029fa typical application features applications description dual 500ma/500ma low dropout, low noise, micropower linear regulator the lt ? 3029 is a dual, micropower, low noise, low drop- out linear regulator. the device operates either with a common input supply or independent input supplies for each channel, over an input voltage range of 1.8v to 20v. each output supplies up to 500ma of output current with a typical dropout voltage of 300mv. quiescent current is well controlled in dropout. with an external 10nf bypass capacitor, output noise is only 20v rms over a 10hz to 100khz bandwidth. designed for use in battery-powered systems, the low 55a quiescent current per channel makes it an ideal choice. in shutdown, quiescent current drops to less than 1a. shutdown control is independent for each channel, allowing for ? exible power management. the lt3029 optimizes stability and transient response with low esr ceramic output capacitors, requiring a minimum of only 3.3f. the regulator does not require the addition of esr, as is common with other regulators. internal circuitry provides reverse-battery protection, reverse-current protection, current limiting with foldback and thermal shutdown. the device is available as an adjustable output voltage device with a 1.215v reference voltage. the lt3029 is offered in the thermally enhanced 16-lead msop and 16-lead, low pro? le (4mm 3mm 0.75mm) dfn packages. 2.5v in to 1.5v/1.8v application n output current: 500ma per channel n low dropout voltage: 300mv n low noise: 20v rms (10hz to 100khz) n low quiescent current: 55a per channel n wide input voltage range: 1.8v to 20v (common or independent input supply) n adjustable output: 1.215v reference voltage n very low quiescent current in shutdown: <1a per channel n stable with 3.3f minimum output capacitor n stable with ceramic, tantalum or aluminum electrolytic capacitors n reverse-battery and reverse output-to-input protection n current limit with foldback and thermal shutdown n tracking/sequencing capability: compatible with ltc292x power supply tracking ics n thermally enhanced 16-lead msop and 16-lead (4mm 3mm) dfn packages n general purpose linear regulator n battery-powered systems n microprocessor core/logic supplies n post regulator for switching supplies n tracking/sequencing power supplies dropout voltage vs load current v out1 1.8v 500ma v out2 1.5v 500ma 237k 1% 10nf 3.3f 113k 1% 3029 ta01 out2 adj2 byp2 gnd 237k 1% 10nf 3.3f 54.9k 1% out1 adj1 byp1 lt3029 in1 v in 2.5v 3.3f shdn1 in2 shdn2 output current (ma) 0 dropout voltage (mv) 400 350 300 250 200 150 100 50 0 400 3029 ta01b 100 200 300 500 50 450 150 250 350 t j = 25c l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners.
lt3029 2 3029fa absolute maximum ratings in1, in2 pin voltage ................................................22v out1, out2 pin voltage .........................................22v input-to-output differential voltage ........................22v adj1, adj2 pin voltage ............................................9v byp1, byp2 pin voltage ........................................0.6v shdn1 , shdn2 pin voltage ..................................22v output short-circuit duration .......................... inde? nite (note 1) 16 15 14 13 12 11 10 9 17 gnd 1 2 3 4 5 6 7 8 adj1 shdn1 in1 in1 in2 in2 shdn2 adj2 byp1 nc out1 out1 gnd out2 out2 byp2 top view de package 16-lead ( 4mm s 3mm ) plastic dfn t jmax = 125c, ja = 38c/w, jc = 4.3c/w exposed pad (pin 17) is gnd, must be soldered to pcb gnd adj1 shdn1 in1 in1 in2 in2 shdn2 adj2 byp1 nc out1 out1 gnd out2 out2 byp2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 top view mse package 16-lead plastic msop 17 gnd t jmax = 125c (lt3029e/lt3029i, lt3029mp), ja = 37c/w, jc : 5c/w to 10c/w t jmax = 150c (lt3029h), ja = 37c/w, jc : 5c/w to 10c/w exposed pad (pin 17) is gnd, must be soldered to pcb gnd pin configuration order information lead free finish tape and reel part marking* package description temperature range lt3029ede#pbf lt3029ede#trpbf 3029 16-lead (4mm 3mm) plastic dfn C40c to 125c lt3029ide#pbf lt3029ide#trpbf 3029 16-lead (4mm 3mm) plastic dfn C40c to 125c lt3029emse#pbf lt3029emse#trpbf 3029 16-lead plastic msop C40c to 125c lt3029imse#pbf lt3029imse#trpbf 3029 16-lead plastic msop C40c to 125c lt3029hmse#pbf lt3029hmse#trpbf 3029 16-lead plastic msop C40c to 150c lt3029mpmse#pbf lt3029mpmse#trpbf 3029 16-lead plastic msop C55c to 125c lead based finish tape and reel part marking* package description temperature range lt3029ede lt3029ede#tr 3029 16-lead (4mm 3mm) plastic dfn C40c to 125c lt3029ide lt3029ide#tr 3029 16-lead (4mm 3mm) plastic dfn C40c to 125c lt3029emse lt3029emse#tr 3029 16-lead plastic msop C40c to 125c lt3029imse lt3029imse#tr 3029 16-lead plastic msop C40c to 125c lt3029hmse lt3029hmse#tr 3029 16-lead plastic msop C40c to 150c lt3029mpmse lt3029mpmse#tr 3029 16-lead plastic msop C55c to 125c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/ operating junction temperature (notes 2, 12) lt3029e ............................................. C40c to 125c lt3029i .............................................. C40c to 125c lt3029h ............................................ C40c to 150c lt3029mp.......................................... C55c to 125c storage temperature range ................... C65c to 150c lead temperature (soldering, 10 sec) (msop only) ..................................................... 300c
lt3029 3 3029fa electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3029 is tested and speci? ed under pulse load conditions such that t j t a . the lt3029e is 100% tested at t a = 25c. performance of the lt3029e over the full C40c to 125c operating junction temperature range is assured by design, characterization and correlation with statistical process controls. the lt3029i is guaranteed over the full C40c to 125c operating junction temperature range. the lt3029mp is 100% tested and guaranteed over the C55c to 125c operating junction temperature range. the lt3029h is tested at 150c operating junction temperature. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125c. parameter conditions min typ max units minimum input voltage (notes 3, 11) i load = 500ma l 1.8 2.3 v adj1, adj2 pin voltage (notes 3, 4, 9) v in = 2v, i load = 1ma 2.3v < v in < 20v, 1ma < i load < 500ma (e, i, mp) 2.3v < v in < 20v, 1ma < i load < 500ma (h) l l 1.203 1.191 1.173 1.215 1.215 1.215 1.227 1.239 1.239 v v v line regulation (note 3) v in = 2v to 20v, i load = 1ma l 0.5 5 mv load regulation (note 3) v in = 2.3v, i load = 1ma to 500ma v in = 2.3v, i load = 1ma to 500ma (e, i, mp) v in = 2.3v, i load = 1ma to 500ma (h) l l 2.5 6 15 32 mv mv mv dropout voltage v in = v out(nominal) (notes 5, 6, 11) i load = 10ma i load = 10ma l 0.11 0.18 0.25 v v i load = 50ma i load = 50ma l 0.16 0.22 0.31 v v i load = 100ma i load = 100ma l 0.2 0.25 0.34 v v i load = 500ma i load = 500ma l 0.3 0.36 0.46 v v gnd pin current (per channel) v in = v out(nominal) (notes 5, 7) i load = 0ma i load = 1ma i load = 50ma i load = 100ma i load = 250ma i load = 500ma l l l l l l 55 90 1.1 2 4.3 10 150 250 2 3.5 8 16 a a ma ma ma ma output voltage noise c out = 10f, c byp = 10nf, i load = 500ma, bw = 10hz to 100khz 20 v rms adj1/adj2 pin bias current adj1, adj2 (notes 3, 8) 30 100 na shutdown threshold v out = off to on v out = on to off l l 0.20 0.45 0.40 1.1 v v shdn1/shdn2 pin current (note 10) v shdn1 , v shdn2 = 0v v shdn1 , v shdn2 = 20v l l 0 0.6 0.5 3 a a quiescent current in shutdown (per channel) v in = 6v, v shdn1 = 0v, v shdn2 = 0v 0.01 0.1 a ripple rejection v in = 2.715v (avg), v ripple = 0.5v p-p , f ripple = 120hz, i load = 500ma 55 67 db current limit (note 9) v in = 7v, v out = 0v v in = 2.3v, v out = C0.1v l 520 1.5 a ma input reverse leakage current v in = C20v, v out = 0v l 1ma reverse output current v out = 1.215v, v in = 0v 0.5 10 a the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. (note 2) note 3: the lt3029 is tested and speci? ed for these conditions with the adj1/adj2 pin connected to the corresponding out1/out2 pin. note 4: maximum junction temperature limits operating conditions. the regulated output voltage speci? cation does not apply for all possible combinations of input voltage and output current. when operating at maximum input voltage, limit the output current range. when operating at maximum output current, limit the input voltage range. note 5: to satisfy minimum input voltage requirements, the lt3029 is tested and speci? ed for these conditions with an external resistor divider (two 243k resistors) for an output voltage of 2.437v. the external resistor divider adds 5a of dc load on the output. note 6: dropout voltage is the minimum input to output voltage differential needed to maintain regulation at a speci? ed output current. in dropout, the output voltage equals: v in C v dropout .
lt3029 4 3029fa typical performance characteristics typical dropout voltage guaranteed dropout voltage dropout voltage vs temperature quiescent current (per channel) electrical characteristics note 7: gnd pin current is tested with v in = 2.437v and a current source load. this means the device is tested while operating in its dropout region or at the minimum input voltage speci? cation. this is the worst-case gnd pin current. the gnd pin current decreases slightly at higher input voltages. total gnd pin current equals the sum of output 1 and output 2 gnd pin currents. note 8: adj1/adj2 pin bias current ? ows into the pin. note 9: the lt3029 contains current limit foldback circuitry. see the typical performance characteristics for current limit as a function of the v in C v out differential voltage. note 10: shdn1/ shdn2 pin current ? ows into the pin. note 11: the lt3029 minimum input voltage speci? cation limits dropout voltage under some output voltage/load conditions. see the curve of minimum input voltage in the typical performance characteristics. note 12: the lt3029 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature exceeds the maximum operating junction temperature when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. output current (ma) 500 450 400 350 300 250 200 150 100 50 0 dropout voltage (mv) 3029 g01 0 50 100 150 200 250 300 350 400 450 500 t j = 150c t j = 25c t j = 125c t j = C55c output current (ma) 500 450 400 350 300 250 200 150 100 50 0 guaranteed dropout voltage (mv) 3029 g02 0 50 100 150 200 250 300 350 400 450 500 t j = 150c t j = 25c = test points temperature (c) 500 450 400 350 300 250 200 150 100 50 0 dropout voltage (mv) 3029 g03 C75 C50 C25 0 25 50 75 100 125 150 175 i l = 500ma i l = 100ma i l = 250ma i l = 50ma i l = 10ma i l = 1ma temperature (c) quiescent current (a) 3029 g04 C75 C50 C25 0 25 50 75 100 125 150 175 v in = 6v r l = 243k, i l = 5a 150 125 100 75 50 25 0 v shdn = v in t j = 25c, unless otherwise noted.
lt3029 5 3029fa adj1 or adj2 pin voltage quiescent current (per channel) typical performance characteristics gnd pin current (per channel) gnd pin current (per channel) gnd pin current vs i load shdn1 or shdn2 pin threshold (on-to-off) temperature (c) adj pin voltage (v) 3029 g05 C75 C50 C25 0 25 50 75 100 125 150 175 i l = 1ma 1.239 1.233 1.227 1.221 1.215 1.209 1.203 1.197 1.191 input voltage (v) 160 140 120 100 80 60 40 20 0 quiescent current (a) 3029 g06 0246 8 10 12 14 16 18 20 t j = 25c r l = 243k v out = 1.215v v shdn = v in v shdn = 0v input voltage (v) gnd pin current (ma) 3029 g07 0123 4 5 67 8910 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 t j = 25c for v out = 1.215v r l = 24.3, i l = 50ma r l = 1.215k, i l = 1ma r l = 121.5, i l = 10ma input voltage (v) gnd pin current (ma) 3029 g08 0123 4 5 67 8910 16 14 12 10 8 6 4 2 0 t j = 25c for v out = 1.215v r l = 2.43, i l = 500ma r l = 12.15, i l = 100ma r l = 4.05, i l = 300ma output current (ma) gnd pin current (ma) 3029 g09 0 50 100 150 200 250 300 350 400 450 500 t j = 25c v in = v out(nominal) + 1v 16 14 12 10 8 6 4 2 0 temperature (c) shdn pin threshold (v) 3029 g10 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 i l = 1ma C75 C50 C25 0 25 50 75 100 125 150 175 t j = 25c, unless otherwise noted.
lt3029 6 3029fa typical performance characteristics current limit temperature (c) current limit (a) 3029 g16 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 v in = 7v v out = 0v C75 C50 C25 0 25 50 75 100 125 150 175 current limit input voltage (v) current limit (a) 3029 g15 0246 8 10 12 14 16 18 20 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 v out = 0v t j = 150c t j = 25c t j = C55c t j = 125c shdn1 or shdn2 pin input current adj1 or adj2 pin bias current temperature (c) shdn pin input current (a) 3029 g13 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 v shdn = 20v C75 C50 C25 0 25 50 75 100 125 150 175 temperature (c) adj pin bias current (na) 3029 g14 C75 C50 C25 0 25 50 75 100 125 150 175 150 135 120 105 90 75 60 45 30 15 0 shdn1 or shdn2 pin threshold (off-to-on) shdn1 or shdn2 pin input current temperature (c) shdn pin threshold (v) 3029 g11 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 C75 C50 C25 0 25 50 75 100 125 150 175 i l = 1ma i l = 500ma shdn pin voltage (v) shdn pin input current (a) 3029 g12 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0246 8 10 12 14 16 18 20 t j = 25c t j = 25c, unless otherwise noted.
lt3029 7 3029fa reverse current input ripple rejection input ripple rejection input ripple rejection minimum input voltage channel-to-channel isolation temperature (c) reverse current (a) 3029 g17 300 270 240 210 180 150 120 90 60 30 0 v in = 0v v adj = v out = 1.215v i adj flows into adj pin to gnd pin i out flows into out pin to in pin C75 C50 C25 0 25 50 75 100 125 150 175 i adj i out frequency (hz) ripple rejection (db) 100 1k 10k 100k 1m 10m 3029 g18 10 40 50 60 70 80 30 20 10 0 90 100 t j = 25c i l = 500ma v in = v out(nominal) +1v + 50mv rms ripple c byp = 0 c out = 10f c out = 3.3f frequency (hz) ripple rejection (db) 100 1k 10k 100k 1m 10m 3029 g19 10 40 50 60 70 80 30 20 10 0 90 100 t j = 25c i l = 500ma v in = v out(nominal) +1v + 50mv rms ripple c out = 10f c byp = 0.01f c byp = 1000pf c byp = 100pf temperature (c) ripple rejection (db) 3029 g20 100 90 80 70 60 50 40 30 20 10 0 v in = v out(nominal) + 1.5v + 0.5v p-p ripple f = 120hz i l = 500ma C75 C50 C25 0 25 50 75 100 125 150 175 temperature (c) minimum input voltage (v) 3029 g21 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 C75 C50 C25 0 25 50 75 100 125 150 175 i l = 1ma i l = 500ma v out = 1.215v frequency (hz) channel-to-channel isolation (db) 100 1k 10k 100k 1m 10m 3029 g22 10 40 50 60 70 80 30 20 10 0 90 100 given channel is tested with 50mv rms signal on opposing channel, both channels delivering full current t j = 25c typical performance characteristics t j = 25c, unless otherwise noted.
lt3029 8 3029fa output noise spectral density (v/? hz) frequency (khz) 0.01 0.1 10 3029 g25 1 v out = 5v v out = v adj t j = 25c c out = 10f c byp = 0 i l = 500ma 0.01 1 10 100 0.1 frequency (khz) output noise spectral density (v/ ? hz) 0.01 1 10 100 3029 g26 0.1 10 1 0.1 0.01 v out = 5v v out =v adj t j = 25c c out = 10f i l = 500ma c byp = 100pf c byp = 0.01f c byp = 1000pf c byp (pf) 10 80 output noise (v rms ) 100 120 160 140 100 1000 10000 3029 g27 60 40 20 0 v out = 5v v out = 1.215v t j = 25c c out = 10f i l = 500ma f bw = 10hz to 100khz channel-to-channel isolation load regulation typical performance characteristics output noise spectral density output noise spectral density rms output noise vs bypass capacitor rms output noise vs load current temperature (c) load regulation (mv) 3029 g24 0 C2 C4 C6 C8 C10 C12 C14 C16 C18 C20 C75 C50 C25 0 25 50 75 100 125 150 175 i l = 1ma to 500ma load current (ma) 0.01 output noise (v rms ) 160 140 120 100 80 60 40 20 0 0.1 1 10010 3029 g28 v out = 5v v out =v adj v out = 5v v out =v adj t j = 25c c out = 10f c byp = 0 c byp = 10nf 50s/div v out1 50mv/div v out2 50mv/div 3029 g23 c out1 = 10f c out2 = 10f c byp1 = c byp2 = 0.01f i l1 = 50ma to 500ma i l2 = 50ma to 500ma v in = 6v, v out1 = v out2 = 5v t j = 25c, unless otherwise noted.
lt3029 9 3029fa 1ms/div v out 100v/div 3029 g29 c out = 10f i l = 500ma v out = 5v 10hz to 100khz output noise, c byp = 0pf 10hz to 100khz output noise, c byp = 100pf 10hz to 100khz output noise, c byp = 1000pf 10hz to 100khz output noise, c byp = 0.01f 1ms/div v out 100v/div 3029 g30 c out = 10f i l = 500ma v out = 5v 1ms/div v out 100v/div 3029 g31 c out = 10f i l = 500ma v out = 5v 1ms/div v out 100v/div 3029 g32 c out = 10f i l = 500ma v out = 5v typical performance characteristics t j = 25c, unless otherwise noted.
lt3029 10 3029fa 200s/div 200mv/div 250ma/div v out deviation load current deviation 3029 g33 v in = 6v c in = 10f c out = 10f i l = 100ma t j = 25c v out = 5v 20s/div 50mv/div 250ma/div v out deviation load current deviation 3029 g34 v in = 6v c in = 10f c out = 10f i l = 100ma t j = 25c v out = 5v 1ms/div v out 1v/div shdn voltage 2v/div 3029 g35 v in = 2.5v c out = 10f r l = 3 i l = 500ma v out = 1.5v 1ms/div v out 1v/div shdn voltage 2v/div 3029 g36 v in = 2.5v c out = 10f r l = 3 i l = 500ma v out = 1.5v typical performance characteristics transient response, c byp = 0pf transient response, c byp = 0.01f start-up time from shutdown, c byp = 0pf start-up time from shutdown, c byp = 0.01f t j = 25c, unless otherwise noted.
lt3029 11 3029fa pin functions byp1/byp2 (pin 1/pin 8): bypass. use the byp1/byp2 pins to bypass the reference of the lt3029 regulator and achieve low output noise performance. internal circuitry clamps the byp1/byp2 pins to 0.6v (one v be ) from ground. a small capacitor from the corresponding output to this pin bypasses the reference to lower the output voltage noise. using a maximum value of 10nf reduces the output voltage noise to a typical 20v rms over a 10hz to 100khz bandwidth. if not used, this pin must be left unconnected. nc (pin 2): no connect. this pin is not connected to any internal circuitry. it may be ? oated, tied to v in or tied to gnd. out1/out2 (pins 3, 4/pins 6, 7): output. the outputs supply power to the loads. a minimum 3.3f output ca- pacitor prevents oscillations on each output. applications with large output load transients require larger values of output capacitance to limit peak voltage transients. see the applications information section for more on output capacitance and reverse output characteristics. gnd (pin 5, 17): ground. the exposed pad (pin 17) of the dfn and msop packages is an electrical connection to gnd. to ensure proper electrical and thermal perfor- mance, solder pin 17 to the pcb ground and tie directly to pin 5. connect the bottom of the output voltage setting resistor divider directly to gnd (pin 5) for optimum load regulation performance. in1/in2 (pins 13, 14/pins 11, 12): inputs. the in1/in2 pins supply power to each channel. the lt3029 requires a bypass capacitor at the in1/in2 pins if located more than six inches away from the main input ? lter capacitor. include a bypass capacitor in battery-powered circuits, as a batterys output impedance rises with frequency. a bypass capacitor in the range of 1f to 10f suf? ces. the lt3029s design withstands reverse voltages on the in pins with respect to ground and the out pins. in the case of a reversed input, which occurs if a battery is plugged in backwards, the lt3029 acts as if a diode is in series with its input. no reverse current ? ows into the lt3029 and no reverse voltage appears at the load. the device protects itself and the load. shdn1 / shdn2 (pin 15/pin 10): shutdown. pulling the shdn1 or shdn2 pin low puts its corresponding lt3029 channel into a low power state and turns its output off. the shdn1 and shdn2 pins are completely independent of each other, and each shdn pin only affects operation on its corresponding channel. drive the shdn1 and shdn2 pins with either logic or an open collector/drain with pull-up resistors. the resistors supply the pull-up current to the open collectors/drains and the shdn1 or shdn2 current, typically less than 1a. if unused, connect the shdn1 and shdn2 to their corresponding in pins. each channel will be in its low power shutdown state if its corresponding shdn pin is not connected. adj1/adj2: (pin 16/pin 9) adjust pin. these are the error ampli? er inputs. these pins are internally clamped to 9v. a typical input bias current of 30na ? ows into the pins (see curve of adj1/adj2 pin bias current vs temperature in the typical performance characteristics section). the adj1 and adj2 pin voltage is 1.215v referenced to ground and the output voltage range is 1.215v to 19.5v.
lt3029 12 3029fa the lt3029 is a dual 500ma/500ma low dropout regulator with independent inputs, micropower quiescent current and shutdown. the device supplies up to 500ma from each channels output at a typical dropout voltage of 300mv. the two regulators share a common gnd pin and are thermally coupled. however, the two inputs and outputs of the lt3029 operate independently. each channel can be shut down independently, but a thermal shutdown fault on either channel shuts off the output on both channels. the addition of a 10nf reference bypass capacitor lowers output voltage noise to 20v rms over a 10hz to 100khz bandwidth. additionally, the reference bypass capacitor improves transient response of the regulator, lowering the settling time for transient load conditions. the low operating quiescent current (55a per channel) drops to less than 1a in shutdown. in addition to the low quies- cent current, the lt3029 regulator incorporates several protection features that make it ideal for use in battery- powered systems. most importantly, the device protects itself against reverse input voltages. current limiting with foldback necessitates a minimum load current of 20a for input/output voltage differentials of more than 10v to keep the output regulated. adjustable operation each of the lt3029s channels has an output voltage range of 1.215v to 19.5v. figure 1 illustrates that output voltage is set by the ratio of two external resistors. the device regulates the output to maintain the corresponding adj pin voltage at 1.215v referenced to ground. r1s current equals 1.215v/r1. r2s current equals r1s current plus the adj pin bias current. the adj pin bias current, 30na at 25c, ? ows through r2 into the adj pin. use the formula in figure 1 to calculate output voltage. linear technology recommends that the value of r1 be less than 243k to minimize errors in the output voltage due to the adj pin bias current. in shutdown, the output turns off and the divider current is zero. curves of adj pin voltage vs temperature and adj pin bias current vs temperature appear in the typical performance characteristics section. applications information figure 1. adjustable operation in1/in2 3029 f01 c lt3029 out1/out2 v in v out adj1/adj2 gnd r1 r2 linear technology tests and speci? es each lt3029 channel with its adj pin tied to the corresponding out pin for a 1.215v output voltage. speci? cations for output voltages greater than 1.215v are proportional to the ratio of desired output voltage to 1.215v: v out 1.215v for example, load regulation on either output for an output current change of 1ma to 500ma is typically C2.5mv at v out = 1.215v. at v out = 2.5v, load regulation is: 2.5v 1.215v ?( ? 2.5mv) =? 5.14mv table 1 shows 1% resistor divider values for some com- mon output voltages with a resistor divider current of approximately 5a. table 1. output voltage resistor divider values v out (v) r1 (k) r2 (k) 1.5 237 54.9 1.8 237 113 2.5 243 255 3 232 340 3.3 210 357 5 200 619 v out = 1.215v 1 + r2 r1 ? ? ? ? ? ? + i adj () r2 () v adj = 1.215v i adj = 30na at 25 c output range = 1.215v to 19.5v
lt3029 13 3029fa applications information bypass capacitance and low noise performance using a bypass capacitor connected between a channels byp pin and its corresponding out pin signi? cantly low- ers lt3029 output voltage noise, but is not required in all applications. linear technology recommends a good quality low leakage capacitor. this capacitor bypasses the regulators reference, providing a low frequency noise pole. a 10nf bypass capacitor introduces a noise pole that decreases output voltage noise to as low as 20v rms . using a bypass capacitor provides the added bene? t of improving transient response. with no bypass capacitor, and a 10f output capacitor, a 100ma to 500ma load step settles to within 1% of its ? nal value in approximately 100s. with the addition of a 10nf bypass capacitor and evaluating the same load step, output voltage excursion stays within 1% (see transient response in the typical performance characteristics section). using a bypass capacitor makes regulator start-up time proportional to the value of the bypass capacitor. for example, a 10nf bypass capacitor and 10f output capacitor slow start-up time to 15ms. output capacitance and transient response the lt3029 design is stable with a wide range of output capacitors. the esr of the output capacitor affects stabil- ity, most notably with small capacitors. linear technology recommends a minimum output capacitor of 3.3f with an esr of 3, or less, to prevent oscillations. the lt3029 is a micropower device, and output transient response is a function of output capacitance. larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes. ceramic capacitors require extra consideration. manufac- turers make ceramic capacitors with a variety of dielectrics, each with different behavior across temperature and applied voltage. the most common dielectrics specify the eia temperature characteristic codes of z5u, y5v, x5r and x7r. z5u and y5v dielectrics provide high c-v products in a small package at low cost, but exhibit strong voltage and temperature coef? cients, as shown in figures 2 and 3. when used with a 5v regulator, a 16v 10f y5v capacitor can exhibit an effective value as low as 1f to 2f for the applied dc bias voltage and over the operat- ing temperature range. x5r and x7r dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. the x7r type has better stability across temperature, while the x5r is less expensive and is available in higher values. dc bias voltage (v) change in value (%) 3029 f02 20 0 C20 C40 C60 C80 C100 0 4 8 10 26 12 14 x5r y5v 16 both capacitors are 16v, 1210 case size, 10f temperature (c) C50 40 20 0 C20 C40 C60 C80 C100 25 75 3029 f03 C25 0 50 100 125 y5v change in value (%) x5r both capacitors are 16v, 1210 case size, 10f figure 2. ceramic capacitor dc bias characteristics figure 3. ceramic capacitor temperature characteristics
lt3029 14 3029fa applications information exercise care even when using x5r and x7r capacitors; the x5r and x7r codes only specify operating temperature range and maximum capacitance change over temperature. capacitance change due to dc bias (voltage coef? cient) with x5r and x7r capacitors is better than with y5v and z5u capacitors, but can still be signi? cant enough to drop capacitor values below appropriate levels. capacitor dc bias characteristics tend to improve as case size increases. linear technology recommends verifying expected versus actual capacitance values at operating voltage in situ for an application. voltage and temperature coef? cients are not the only sources of problems. some ceramic capacitors have a piezoelectric response. a piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric accelerometer or micro- phone works. for a ceramic capacitor, the stress can be induced by vibrations in the system or thermal transients. the resulting voltages produced can cause appreciable amounts of noise, especially when a ceramic capacitor is used for noise bypassing. a ceramic capacitor produced figure 4s trace in response to light tapping from a pencil. similar vibration induced behavior can masquerade as increased output voltage noise. figure 4. noise resulting from tapping on a ceramic capacitor v out 500v/div 3029 f04 100ms/div c out = 10f c byp = 0.01f i load = 500ma thermal considerations the lt3029s power handling capability limits the maximum rated junction temperature (125c, lt3029e/lt3029i/ lt3029mp or 150c, lt3029h). two components comprise the power dissipated by each channel: 1. output current multiplied by the input/output voltage differential: (i out )(v in C v out ), and 2. gnd pin current multiplied by the input voltage: (i gnd )(v in ). ground pin current is found by examining the gnd pin current curves in the typical performance characteristics section. power dissipation for each channel equals the sum of the two components listed above. total power dissipation for the lt3029 equals the sum of the power dissipated by each channel. the lt3029s internal thermal shutdown circuitry protects both channels of the device if either channel experiences an overload or fault condition. activation of the thermal shutdown circuitry turns both channels off. if the overload or fault condition is removed, both outputs are allowed to turn back on. for continuous normal conditions, do not exceed the maximum junction temperature rating of 125c (lt3029e/lt3029i/lt3029mp) or 150c (lt3029h). carefully consider all sources of thermal resistance from junction-to-ambient, including additional heat sources mounted in proximity to the lt3029. for surface mount devices, use the heat spreading capabilities of the pc board and its copper traces to accomplish heat sinking. copper board stiffeners and plated through-holes can also spread the heat generated by power devices. the following tables list thermal resistance as a function of copper area in a ? xed board size. all measurements were taken in still air on a four-layer fr-4 board with 1oz solid internal planes, and 2oz external trace planes with a total board thickness of 1.6mm. for further information on thermal resistance and using thermal information, refer to jedec standard jesd51, notably jesd51-12.
lt3029 15 3029fa applications information table 2. de package, 16-lead dfn copper area thermal resistance (junction-to-ambient) topside * backside board area 2500mm 2 2500mm 2 2500mm 2 36c/w 1000mm 2 2500mm 2 2500mm 2 37c/w 225mm 2 2500mm 2 2500mm 2 38c/w 100mm 2 2500mm 2 2500mm 2 40c/w *device is mounted on topside. table 3. mse package, 16-lead msop copper area board area thermal resistance (junction-to-ambient) topside * backside 2500mm 2 2500mm 2 2500mm 2 35c/w 1000mm 2 2500mm 2 2500mm 2 36c/w 225mm 2 2500mm 2 2500mm 2 37c/w 100mm 2 2500mm 2 2500mm 2 39c/w *device is mounted on topside. the junction-to-case thermal resistance ( jc ), measured at the exposed pad on the back of the die, is 4.3c/w for the dfn package, and 5c/w to 10c/w for the msop package. calculating junction temperature example: channel 1s output voltage is set to 1.8v. chan- nel 2s output voltage is set to 1.5v. each channels input voltage is 2.5v. each channels output current range is 0ma to 500ma. the application has a maximum ambient temperature of 50c. what is the lt3029s maximum junction temperature? the power dissipated by each channel equals: i out(max) (v in C v out ) + i gnd (v in ) where for each output: i out(max) = 500ma v in = 2.5v i gnd at (i out = 500ma, v in = 2.5v) = 8.5ma so, for output 1: p = 500ma (2.5v C 1.8v) + 8.5ma (2.5v) = 0.37w for output 2: p = 500ma (2.5v C 1.5v) + 8.5ma (2.5v) = 0.52w the thermal resistance is in the range of 35c/w to 40c/w, depending on the copper area. so, the junction temperature rise above ambient temperature approximately equals: (0.37w + 0.52w) 39c/w = 34.7c the maximum junction temperature then equals the maxi- mum ambient temperature plus the maximum junction temperature rise above ambient temperature, or: t jmax = 50c + 34.7c = 84.7c protection features the lt3029 regulator incorporates several protection fea- tures that make it ideal for use in battery-powered circuits. in addition to the normal protection features associated with monolithic regulators, such as current limiting and thermal limiting, the device protects itself against reverse input voltages and reverse voltages from output to input. the two regulators have independent inputs, a common gnd pin and are thermally coupled. however, the two channels of the lt3029 operate independently. each channels output can be shut down independently, and a fault condition on one output does not affect the other output electrically, unless the thermal shutdown circuitry is activated. current limit protection and thermal overload protection protect the device against current overload conditions at each output of the lt3029. for normal operation, do not allow the junction temperature to exceed 125c (lt3029e/ lt3029i/lt3029mp) or 150c (lt3029h). the typical ther- mal shutdown temperature threshold is 165c and the circuitry incorporates approximately 5c of hysteresis. each channels input withstands reverse voltages of 22v. current ? ow into the device is limited to less than 1ma (typically less than 100a) and no negative voltage appears at the respective channels output. the device protects both itself and the load against batteries that are plugged in backwards. the lt3029 incurs no damage if either channels output is pulled below ground. if the input is left open-circuit, or grounded, the output can be pulled below ground by 22v. the output acts like an open circuit, and no current ? ows from the output. however, current ? ows in (but is limited by) the external resistor divider that sets the output voltage.
lt3029 16 3029fa applications information the lt3029 incurs no damage if either adj pin is pulled above or below ground by 9v. if the input is left open circuit or grounded, the adj pins perform like an open circuit down to C1.5v, and then like a 1.2k resistor down to C9v when pulled below ground. when pulled above ground, the adj pins perform like an open circuit up to 0.5v, then like a 5.7k resistor up to 3v, then like a 1.8k resistor up to 9v. in situations where an adj pin connects to a resistor divider that would pull the pin above its 9v clamp volt- age if the output is pulled high, the adj pin input current must be limited to less than 5ma. for example, assume a resistor divider sets the regulated output voltage to 1.5v, and the output is forced to 20v. the top resistor of the resistor divider must be chosen to limit the current into the adj pin to less than 5ma when the adj pin is at 9v. the 11v difference between the out and adj pins divided by the 5ma maximum current into the adj pin yields a minimum top resistor value of 2.2k. in circuits where a backup battery is required, several different input/output conditions can occur. the output voltage may be held up while the input is either pulled to ground, pulled to some intermediate voltage or is left open-circuit. current ? ow back into the output follows the curve shown in figure 5. if either of the lt3029s in pins is forced below its cor- responding out pin, or the out pin is pulled above its corresponding in pin, input current for that channel typi- cally drops to less than 2a. this occurs if the in pin is connected to a discharged (low voltage) battery, and either a backup battery or a second regulator circuit holds up the output. the state of that channels shdn pin has no effect on the reverse output current if the output is pulled above the input. overload recovery like many ic power regulators, the lt3029 has safe operating area (soa) protection. the safe area protec- tion decreases current limit as input-to-output voltage increases and keeps the power transistor inside a safe operating region for all values of input-to-output voltage. the protective design provides some output current at all values of input-to-output voltage up to the speci? ed maximum operational input voltage of 20v. when power is ? rst applied, as input voltage rises, the output follows the input, allowing the regulator to start-up into very heavy loads. during start-up, as the input voltage is rising, the input-to-output voltage differential is small, allowing the regulator to supply large output currents. with a high input voltage, an event can occur wherein removal of an output short will not allow the output to recover. the event occurs with a heavy output load when the input voltage is high and the output voltage is low. common situations occur immediately after the removal of a short-circuit or if the shutdown pin is pulled high after the input voltage has already been turned on. the load line intersects the output current curve at two points creating two stable output operating points for the regulator. with this double intersection, the input power supply may need to be cycled down to zero and brought up again to make the output recover. figure 5. reverse output current output voltage (v) reverse current (ma) 3029 f05 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 t j = 25c v in = 0v v adj = v out i adj flows into adj pin to gnd pin i out flows into out pin to in pin 0123 4 5 6789 i adj i out
lt3029 17 3029fa package description de package 16-lead plastic dfn (4mm 3mm) (reference ltc dwg # 05-08-1732 rev ?) 3.00 0.10 (2 sides) 4.00 0.10 (2 sides) note: 1. drawing proposed to be made variation of version (wged-3) in jedec package outline mo-229 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.70 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 3.15 ref 1.70 0.05 1 8 16 9 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (de16) dfn 0806 rev ? pin 1 notch r = 0.20 or 0.35 45 chamfer 3.15 ref recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 2.20 0.05 0.70 0.05 3.60 0.05 package outline 0.25 0.05 3.30 0.05 3.30 0.10 0.45 bsc 0.23 0.05 0.45 bsc
lt3029 18 3029fa package description msop (mse16) 0608 rev a 0.53 p 0.152 (.021 p .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 C?0.27 (.007 C .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16 16151413121110 12345678 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0o C 6o typ detail a detail a gauge plane 5.23 (.206) min 3.20 C 3.45 (.126 C .136) 0.889 p 0.127 (.035 p .005) recommended solder pad layout 0.305 p 0.038 (.0120 p .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 p 0.102 (.112 p .004) 2.845 p 0.102 (.112 p .004) 4.039 p 0.102 (.159 p .004) (note 3) 1.651 p 0.102 (.065 p .004) 1.651 p 0.102 (.065 p .004) 0.1016 p 0.0508 (.004 p .002) 3.00 p 0.102 (.118 p .004) (note 4) 0.280 p 0.076 (.011 p .003) ref 4.90 p 0.152 (.193 p .006) mse package 16-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1667 rev a) detail b detail b corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref
lt3029 19 3029fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 3/11 added overload recovery section to applications information 16
lt3029 20 3029fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com linear technology corporation 2010 lt 0311 rev a ? printed in usa related parts typical application part number description comments lt1761 100ma, low noise micropower ldo v in : 1.8v to 20v, v out(min) = 1.22v, v do = 0.3v, i q = 20a, i sd < 1a, low noise < 20v rms , stable with 1f ceramic capacitors, thinsot tm package lt1763 500ma, low noise micropower ldo v in : 1.8v to 20v, v out(min) = 1.22v, v do = 0.3v, i q = 30a, i sd < 1a, low noise < 20v rms , s8 and dfn packages lt1963/ lt1963a 1.5a, low noise, fast transient response ldos v in : 2.1v to 20v, v out(min) = 1.21v, v do = 0.34v, i q = 1ma, i sd < 1a, low noise: < 40v rms , a version stable with ceramic capacitors; dd, to220-5, sot223, s8 and tssop packages lt1964 200ma, low noise micropower, negative ldo v in : C1.9v to C20v, v out(min) = C1.22v, v do = 0.34v, i q = 30a, i sd = 3a, low noise: <30v rms , stable with ceramic capacitors, thinsot package lt1965 1.1a, low noise ldo v in : 1.8v to 20v, v out(min) = 1.20v, v do = 0.31v, i q = 0.5ma, i sd < 1a, low noise: <40v rms , stable with ceramic capacitors; 3mm 3mm dfn, ms8e, dd-pak and to-220 packages lt3020 100ma, low voltage vldo v in : 0.9v to 10v, v out(min) = 0.20v, v do = 0.15v, i q = 120a, i sd < 3a; 3mm 3mm dfn and ms8 packages lt3021 500ma, low voltage vldo v in : 0.9v to 10v, v out(min) = 0.20v, v do = 0.16v, i q = 120a, i sd < 3a; 5mm 5mm dfn and so8 packages lt3023 dual 100ma, low noise, micropower ldo v in : 1.8v to 20v, v out(min) = 1.22v, v do = 0.30v, i q = 40a, i sd < 1a; dfn and ms10e packages lt3024 dual 100ma/500ma, low noise, micropower ldo v in : 1.8v to 20v, v out(min) = 1.22v, v do = 0.30v, i q = 60a, i sd < 1a; dfn and tssop-16e packages ltc3025 300ma, low voltage micropower vldo v in : 0.9v to 5.5v, low i q : 54a, low noise < 80v rms , 45mv dropout voltage; 2mm 2mm 6-lead dfn package ltc3026 1.5a, low input voltage vldo v in : 1.14v to 5.5v, low i q : 950a, low noise < 110v rms , 100mv dropout voltage; 10-lead 3mm 3mm dfn and ms10e packages lt3027 dual 100ma, low noise, micropower ldo with independent inputs v in : 1.8v to 20v, v out(min) = 1.22v, v do = 0.30v, i q = 50a, i sd < 1a; dfn and ms10e packages lt3028 dual 100ma/500ma, low noise, micropower ldo with independent inputs v in : 1.8v to 20v, v out(min) = 1.22v, v do = 0.32v, i q = 60a, i sd < 1a; dfn and tssop-16e packages LT3080/ LT3080-1 1.1a, parallelable, low noise ldo v in : 1.2v to 36v, v out : 0v to 35.7v, low noise < 40v rms , 300mv dropout voltage (2-supply operation), current-based reference with 1-resistor v out set, directly parallelable (no op amp required), stable with ceramic capacitors; to-220, sot-223, ms8e and 3mm 3mm dfn packages thinsot is a trademark of linear technology corporation. v out1 1.8v 500ma v out2 1.5v 500ma 237k 1% 10nf 3.3f 113k 1% 3029 ta02 out2 adj2 byp2 gnd 237k 1% 10nf 3.3f 54.9k 1% out1 adj1 byp1 lt3029 ltc2923 in1 v cc 3.3f shdn1 in2 shdn2 sdo fb2 gnd ramp gate fb1 on track1 rampbuf track2 2.5v 3.3v 3.3f 63.4k 1% 54.9k 1% 90.9k 1% 113k 1% 0.1f 3.3v c gate 0.1f on off 1m coincident tracking supply application 10ms/div v out1 v out2 500mv/div 3029 ta02b

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